Multiplexing transmission system, receiver apparatus and module, transmitter apparatus for multiplexing transmission

ABSTRACT

Digital signals having respective pieces of frequency information different from each other are bundled, and transmitted at high speed. On receiving side, digital signals retaining the respective pieces of frequency information are recovered and separated. Transmitter apparatus divides pieces of transmission data that have the different pieces of frequency information and correspond to respective input channels into data blocks having a fixed length, as valid data, and subsequently multiplexes the data blocks corresponding to the respective input channels and outputs the multiplexed data to a transmission path. A receiver apparatus divides data string received into data flows and subsequently restores the transmission data, from the data blocks consecutive in each data flow and stores the restored data, and outputs transmission data corresponding to the respective data flows in synchronization with clocks generated for these data flows.

CLAIM OF PRIORITY

The present application claims priority from Japanese patent applicationJP 2011-199911 filed on Sep. 13, 2011, the content of which is herebyincorporated by reference into this application.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to multiplexing transmission thattransmits data via a transmission path.

2. Background Art

In recent years, many high speed serial data signals have been used infields of mutually connecting LSIs and PCBs (printed circuit boards)that configure an information processing apparatus. In general, electricdata signals are used for short distance transmission having a signaltransmission distance equal to or less than several centimeters; opticaldata signals are used for long distance transmission having a signaltransmission distance at least one meter. As signal transmission ratesincrease, the distance allowing transmission by electric data signalstends to be shorter and shorter. For instance, as a PCB that uniformizeswirings connecting PCBs to each other in an information processingapparatus (what is called a backplane PCB) has had an improvedtransmission rate of 10 Gbps or more, signals to be used fortransmission has started to shift from electric data signals, which aredifficult to transmit over a long distance, to optical data signals,which allow stable transmission.

The rate of transmission by optical data signals can be increased incomparison with the rate of transmission of electric data signals.Accordingly, the need intensifies for multiplexing many electric datasignals on a PCB into a small number of optical data signals andtransmitting the multiplexed signals. Thus, various techniques formultiplexing signals have been developed.

FIG. 1 shows a conventional multiplexer and de-multiplexer. Amultiplexer circuit (the left in the drawing) used in this conventionalcircuit is required to operate in following conditions.

(1) Immediately before input into a multiplexer disposed at a finalstage, all the data rates (X1 bps, . . . , Xn bps) of n inputs (TxP1, .. . , TxPn) are equal to each other. That is, X1=X2= . . . =Xn.

(2) The phases of all the pieces of bit data are the same as each other.

(3) The data rate of an output of the multiplexer is equal to the sum ofthe data rates of all the inputs. That is, Y=X1×n.

In general, a multiplexer circuit performs a process of converting a lowspeed parallel data signal (synchronization signals having the samespeed and the same phase on all channels) into a high speed serial datasignal. However, the conventional circuit shown in FIG. 1 does not havea mechanism ensuring that the number of an output channel of ade-multiplexer configuring a de-multiplexer circuit (the right in thedrawing) coincides with the number of an input channel of a multiplexercircuit.

This type of mechanism is disclosed in JP Patent Publication (Kokai) No.2000-252942 A. A multiplexer and de-multiplexer described in JP PatentPublication (Kokai) No. 2000-252942 A relates to a multiplexing process(specifically, SONET/SDH protocol) technique on optical data signals. Amultiplexer circuit multiplexes low speed optical data signals togenerate a high speed optical data signal, and a de-multiplexer circuitseparates the high speed optical data signal to recover the initial lowspeed optical data signals.

FIG. 2 shows a configuration of a multiplexer and de-multiplexer circuithaving a synchronization circuit disclosed in JP Patent Publication(Kokai) No. 2000-252942 A. A multiplexer circuit (the left in thedrawing) shown in FIG. 2 terminates a specified protocol of only onechannel among n+1 channels, and inserts a special pattern into thechannel. The input, into which the special pattern has been inserted, ismultiplexed by a (n+1):1 multiplexer into the other n inputs (TxP1, . .. , TxPn). That is, reframing is performed. In the drawing, a circuitused for generating the special pattern is denoted as a patterngenerator.

Meanwhile, a de-multiplexer circuit (the right in the drawing) shown inFIG. 2 performs a special pattern synchronization process on a specifiedchannel among separated n+1 channels. In the drawing, a circuit used forthe special pattern synchronization is denoted as a patternsynchronizer. Through the synchronization process, the de-multiplexercircuit detects the leading position from which a 1:(n+1) de-multiplexerseparates the multiplexed signal. Adoption of this mechanism allows themultiplexer and de-multiplexer shown in FIG. 2 to ensure the matchingrelationship between the numbers of the input channel and the outputchannel (hereinafter, the position of channel).

In the case of the circuit shown in FIG. 1, it is required totemporarily terminate the protocols of all the channels and concatenatedata to multiplex the data. The circuit shown in FIG. 2 can keep thetermination of the protocol to be only one channel. Accordingly, theapparatus of the circuit shown in FIG. 2 can be reduced in scale incomparison with the circuit shown in FIG. 1.

There is another method that temporally multiplexes packet data or framedata corresponding to inputs having different data rates and transmitsthe multiplexed data. A typical conventional art is a frame multiplexingapparatus standardized by the IEEE802 Committee (IEEE Std 802.3-2008).This frame multiplexing temporarily stores the frames of the channelshaving different data rates in a buffer, and subsequently reads theframes at the rate of an output channel, thereby realizing amultiplexing process on the channels having different data rates.

As described above, data transmission executed in an apparatus isrequired to handle many transmission channels. Accordingly, theapparatus and LSIs related to the data transmission are specificallyrequired to be downsized.

However, in this type of use, the data rates of input channels to bemultiplexed vary according to use situations. Accordingly, it isdifficult to synchronize the data rates of all the channels input intothe multiplexer. Furthermore, the data rates of the channels output fromthe de-multiplexer are required to completely coincide with the datarate of the respective corresponding input channels on the multiplexerside, in order to realize complete data transmission independent of thecontent of data to be transmitted on each channel without data loss.Thus, a realization method satisfying these conditions is required.

However, the multiplexer and de-multiplexer (FIG. 2) disclosed in JPPatent Publication (Kokai) No. 2000-252942 A cannot satisfy theconditions. This is because the circuit shown in FIG. 2 assumes that therates of input channels are the same and realizes a multiplexing processon optical data signals by a simple multiplexer. That is, this isbecause the circuit configuration shown in FIG. 2 is incapable ofmultiplexing inputs having different data rates. Even if a process ofterminating the SONET/SDH protocol is executed on a single channel, therequired circuit scale is large. This is unsuitable for downsizing LSIs.

In contrast, a frame multiplexing apparatus disclosed in IEEE Std802.3-2008 is capable of a multiplexing process of channels havingdifferent data rates.

However, the apparatus of IEEE Std 802.3-2008 is also incapable ofcausing the data rates of the input channel and the data rate of theoutput channel to completely coincide with each other. This is becauseaccommodation of the difference between the data rates by framing losesclock information (clock frequency, frequency jitter, etc.) included indata on each channel at the time of input into the multiplexer.Furthermore, the apparatus of IEEE Std 802.3-2008 assigns destinationsin units of frames and executes a process of dividing data according tothe destinations, in order to ensure data transmission between the inputchannels and the output channels. This necessitates a process ofsearching for a destination for dividing data and a process of storingdata for preventing data congestion. This fact means that the processingtime required for data transmission cannot be strictly ensured. Theaforementioned process requires a much larger circuit than that of theapparatus of JP Patent Publication (Kokai) No. 2000-252942 A.Accordingly, this process is very unsuitable for downsizing LSIs.

Furthermore, the invention disclosed in JP Patent Publication (Kokai)No. 2000-252942 A and the invention disclosed in IEEE Std 802.3-2008cannot be combined together. This is because the apparatus of JP PatentPublication (Kokai) No. 2000-252942 A assumes that the input rates ofchannels be the same and multiplexes data on the channels. In contrast,the apparatus of IEEE Std 802.3-2008 is required to temporarilyterminate the protocols of all channels and subsequently capture framesand execute a multiplexing process. Accordingly, an apparatus combiningboth the inventions leads to a result of losing an advantageous effect(reduction in apparatus scale) due to only one channel being terminatedin JP Patent Publication (Kokai) No. 2000-252942 A. Even if bothinventions are combined together, the data rate of the input channel andthe data rate of the output channel cannot coincide with each other.Accordingly, the problem of IEEE Std 802.3-2008 cannot be solved.

SUMMARY OF THE INVENTION

In view of the technical problems, it is an object of the presentinvention to realize multiplexing transmission technique that canmultiplex data signals (e.g., digital signals that are generatedaccording to clock sources and have different frequency errors and/ordifferent jitter characteristics, and/or digital signals havingdifferent bit rates) having different frequency information andtransmits the multiplexed signals and, on the receiving side, separateand recover the digital signals while retaining frequency information atthe time of multiplexing the digital signals.

Thus, the present inventor proposes a data multiplexer system includinga transmitter apparatus and a receiver apparatus (including a receivermodule) that have a following processing function.

The transmitter apparatus includes: (A1) a plurality of input channels,each of which is capable of receiving transmission data having frequencyinformation different from frequency information of the other inputchannels; (A2) a plurality of block divider that divide transmissiondata corresponding to the respective input channels into data blockshaving a fixed length, as valid data; and (A3) a multiplexer thatmultiplexes the data blocks corresponding to the respective inputchannels and outputs multiplexed data to the transmission path.

The receiver apparatus includes: (B1) a de-multiplexer that divides adata string received via the transmission path into as many data flowsas the input channels on a side of the transmitter apparatus; (B2) aplurality of FIFOs that execute a process of restoring valid data fromthe corresponding data flows and storing the data in respective FIFOmemories, and a process of reading the transmission data from therespective FIFO memories and outputting the data to the correspondingoutput channels; and (B3) a plurality of frequency controllers thatexecute a process of estimating transmission data rates from timeaverage data rates of the respective corresponding data flow, and aprocess of adjusting the frequencies of clocks supplied to thecorresponding FIFOs so as to be equal to the respective estimatedtransmission data rates.

According to the present invention, the transmitter apparatus is capableof multiplexing the data strings on the respective input channels, whileretaining the pieces of frequency information of the pieces oftransmission data on the respective channels. In an analogous manner,the receiver apparatus captures the pieces of frequency informationspecific to the respective data flows and separately adjusts thefrequencies of the clocks when separating the pieces of data from therespective data flows. This allows matching to be ensured between thedata rates on the input channel and the output channel. Objects,configurations and advantageous effects other than those described abovewill become apparent according to the following description onembodiments.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram showing a multiplexer and de-multiplexer including atypical multiplexer circuit and a de-multiplexer circuit.

FIG. 2 is a diagram showing a multiplexer and de-multiplexer including amultiplexer and a de-multiplexer shown in JP Patent Publication (Kokai)No. 2000-252942 A.

FIG. 3 is a diagram showing an example of a configuration of amultiplexer circuit (transmitter apparatus) according to Embodiment 1.

FIG. 4 is a diagram showing an example of a data format used inEmbodiment 1.

FIG. 5 is a diagram showing an example of a configuration of ade-multiplexer circuit (receiver apparatus) according to Embodiment 1.

FIG. 6 is a diagram showing an example of a configuration of a PLL(phase locked loop) circuit used in Embodiment 1.

FIG. 7 is a diagram illustrating an initial sequence of PLL control in afrequency controller according to Embodiment 1.

FIG. 8 is a diagram illustrating an update sequence of the PLL controlin the frequency controller according to Embodiment 1.

FIG. 9 is a diagram showing an example of a configuration of amultiplexer circuit (transmitter apparatus) according to Embodiment 2.

FIG. 10 is a diagram illustrating a block forming process executed in ablock framer.

FIG. 11 is a diagram showing an example of a configuration of ade-multiplexer circuit (receiver apparatus) according to Embodiment 2.

FIG. 12 is a diagram showing an example of a configuration of amultiplexer circuit (transmitter apparatus) according to Embodiment 3.

FIG. 13 is a diagram showing an example of a configuration of ade-multiplexer circuit (receiver apparatus) according to Embodiment 3.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

In the following description, the present invention will be divided intoexamples of modes and embodiments and described, as necessary for thesake of convenience. Without particularly specified, the examples andembodiments are not irrelevant to each other. There may be relationshipwhere one is a variation, an application, detailed description,supplementary description or the like of a part or the entire parts ofthe others. In the following examples of modes and embodiments, whenreferring to the number of elements and the like (including the numberof pieces, a numerical value, amount, range, etc.), except for the caseof being particularly specified and the case of being limited to thespecified number according to the principle, the specified numberimposes no limitation. The number may be more than or less than thespecified number.

Furthermore, in the following examples of modes and embodiments, theconfigurational elements (including element steps etc.) are notnecessarily required, except for the case of being particularlyspecified and the case where it can be considered that it is necessaryaccording to the principle. Likewise, in the following examples of modesand embodiments, when the aforementioned number and the like (includingthe number of pieces, value, amount, range, etc.) are referred to, whatis substantially analogous or similar to the number and the like isincluded, except for the case of being particularly specified and thecase where this is not apparently applied.

Examples of modes and embodiments of the present invention willhereinafter be described in detail with respect to drawings. In all thedrawings for illustrating the examples of modes and embodiments,identical or related symbols are assigned to components having the samefunction. Repetitive description thereof is omitted. In the followingexamples of modes and embodiments, the description on the same oranalogous parts is not repeated in principle without being specificallyrequired.

A. Example of Mode

[Overall Configuration]

First, the conceptual configuration of a data multiplexer system commonto the embodiments will be described. A data multiplexer system includesa transmitter apparatus and a receiver apparatus. The transmitterapparatus includes n CDRs (clock and data recovery), n FIFOs(first-in-first-out buffers), n block framers (block framers), a patterngenerator, a multiplexer, a clock source for an input stage, a PLL forthe input stage, a clock source for an output stage, and a PLL for theoutput stage. The receiver apparatus includes a clock source for aninput stage, a PLL for the input stage, a CDR, a clock divider, ade-multiplexer, a pattern synchronizer, n block de-framers, n FIFOs, aclock source for an output stage, n PLLs, and n frequency controllers.

[Configuration of Transmitter Apparatus]

The transmitter apparatus receives n data signals. The n data signalsmay have frequency information different from each other, or frequencyinformation identical to each other. It is unnecessary that all the ndata signals have different frequency information. Instead, it issufficient that any of the signals has frequency information differentfrom that of the other data signal. Such data signals include, forinstance, data signals generated according to clock sources havingdifferent frequency errors, digital signals generated according to clocksources having different jitter characteristics, and digital signalshaving different bit rates.

The n data signal channels are input into the respective correspondingCDRs. Thus, the number of CDRs is n. Each CDR extracts a clock componentfrom the input data signal, recovers a recovered clock synchronized withthe data signal and bit data synchronized with this clock on the basisof a high frequency clock supplied from the corresponding PLL. The bitdata and the recovered clock are transmitted from the CDR to the FIFO.

The n clock sources for the input stage generate reference clocks havingunique frequencies, and supply the clocks to the respective n CDRs. Then PLLs for the input stage generate clocks having a frequency exactlyconstant times the frequency of the reference clocks supplied from theclock sources, to the respective corresponding CDRs.

The n FIFOs receive the bit data and the recovered clocks from therespective corresponding CDRs, and stores bit data strings in internalFIFO (first in first out) memories in synchronization with the recoveredclocks. The FIFOs read the bit data strings stored in the FIFO memoriesin synchronization with the recovered clocks supplied from the CDRs, andtransmit the strings to the respective corresponding block framers. Whenthe FIFO memory does not store data, the FIFO notifies the block framerthat the FIFO memory is in an empty state. Meanwhile, when the FIFOmemory is full, the FIFO notifies the block framer that the FIFO memoryis full. The clocks used by the n FIFO memories during readout aresynchronized with the clock commonly supplied from the PLL for theoutput stage.

The n block framers read data stored in the respective FIFOs and dividethe data into blocks having a certain size. Each block framer adds aheader identifier (e.g., “10”/“01”), according to which a valid orinvalid status of the block data can be determined, to a payload, on thebasis of the notification of whether the FIFO memory is in the emptystate or the full state, and stores the data. Each block framertransmits the block data having the valid or invalid data to themultiplexer. The pattern generator generates a data string having afixed pattern at a prescribed cycle, and transmits the string to themultiplexer. The multiplexer temporally multiplexes bit strings receivedfrom the n block framers and the pattern generator on a bit-by-bitbasis, and outputs a serial bit string that is (n+1) times faster.

[Configuration of Receiver Apparatus]

Received Data in the form of a serial bit string is input into thereceiver apparatus. The received data is input into the CDR. The CDRextracts a clock component from the input received data, whilerecovering a recovered clock synchronized with the data signal and bitdata synchronized with the clock on the basis of the high frequencyclock supplied from the PLL. The CDR transmits the recovered clock tothe divider and the de-multiplexer, and transmits the recovered data tothe de-multiplexer. Here, the PLL refers to the clock received from theclock source, and generates a clock having a frequency exactly constanttimes the frequency of the clocks. The clock divider generates a dividedclock that is obtained by precisely dividing the recovered clock by afactor n+1, and distributes the generated divided clock to thede-multiplexer, all the block de-framers, all the FIFOs, and the patternsynchronizer.

The de-multiplexer receives a high frequency recovered clock suppliedfrom the CDR, and receives a low frequency recovered clock from theclock divider. The de-multiplexer uses the two recovered clocks toconvert the recovered data in the serial form into that in a parallelform. Here, the de-multiplexer captures the bit data on a bit-by-bitbasis according to the received order. The capturing position can bechanged. The capturing position is supplied from the patternsynchronizer. The de-multiplexer converts the recovered data into n datasignals and one patterned signal. The n block de-framers and the onepattern synchronizer are connected to the de-multiplexer.

The pattern synchronizer receives the bit data captured by thede-multiplexer at intervals of n+1 bits. The pattern synchronizerverifies correlation between the bit data and the specific patterngenerated by the pattern generator of the transmitter apparatus. In thecase where the correlation between the data string being currentlyreceived and the specific pattern is significantly low, the patternsynchronizer issues an instruction of shifting the capturing position inthe de-multiplexer by one bit and verifies the correlation again. Inthis case, if the correlation between data strings is verified for atleast a prescribed time, the capturing position in the de-multiplexer isfixed.

The n block de-framers only captures bit data in a block havinginformation indicating validness (valid block) from the block sequenceinput from the de-multiplexer, and outputs the data to the respectivecorresponding FIFOs. More specifically, the block de-framer finds theheader identifier (“10”/“01”) defined by the block format, anddetermines that the position is a boundary of the block format. Theblock de-framer extracts only the payload in the block having the headeridentifier indicating validness, and transmits the payload to the FIFOon the following stage.

The FIFO stores the valid data received from the block de-framer in theinternal FIFO memory. The FIFO sequentially reads the data stored in theFIFO memory according to the clock supplied from the PLL. When the rateof writing the valid data is equal to the rate of reading the storeddata, increase and decrease of the amount of stored data are averaged tozero. In this case, the FIFO is in a normal state. In contrast, the rateof writing the valid data is higher than the rate of reading the storeddata, the FIFO memory runs out of space. In this case, the FIFO becomesan overflow state (hereinafter, also referred to as “OF”). Meanwhile,the rate of writing the valid data is less than the rate of reading thestored data, data shortage occurs. In this case, the FIFO becomes anunderflow (hereinafter, also referred to a “UF”) state. The FIFOnotifies the frequency controller of status information indicating OF orUF and the current remaining amount of stored data.

The clock source generates a reference clock that is the uniquefrequency. The PLL generates a high frequency clock having a frequencythat is obtained by multiplying the frequency of the reference clockreceived from the clock source by the number of divisions notified fromthe frequency controller. The frequency controller monitors the state ofthe FIFO memory in the FIFO (OF, UF, the remaining amount of storeddata), and controls the frequency of the clock generated in the PLL suchthat the FIFO normally operates (overflow or underflow does not occur).The frequency controller designates the division ratio for controllingthe frequency of the high frequency clock to be generated in the PLL bymeans of a real number.

[Realized Advantageous Effects]

The transmitter apparatus adds the identifier indicating validness tothe block data received from each input channel, while, if the data rateis insufficient for the output band, inserting a block data to which anidentifier indicating invalidness is added. Subsequently, thetransmitter apparatus multiplexes the data strings for transmission thatretain frequency information. Accordingly, the multiplexed data iscreated while the frequency information of each channel is retained.

When the receiver apparatus separates the received multiplexed data,this apparatus captures the frequency information (time average datarate) specific to each channel on the basis of the rate of generatingvalid blocks on each channel and causes the PLL circuit to recover aclock for reading that has the frequency identical to the frequencyconcerned. This allows the matching between the data rate on the outputchannel and the data rate on the input channel to be ensured.

The frequency information is dealt with on each channel. Accordingly,also on the receiving side, the data rate on the output channel can beset on a channel-by-channel basis. That is, adoption of theaforementioned configuration allows the multiplexing process withdifferent data rates to be realized.

The internal operations of the transmitter apparatus and the receiverapparatus are not affected by the content of data to be transmitted andthe protocol. Accordingly, the processing time required for datatransmission on the input channel and data transmission on the outputchannel can be strictly ensured. This simultaneously allows delay intransmission time to be suppressed.

As described above, use of the transmitter apparatus and the receiverapparatus proposed in this specification can realize a multiplexerapparatus capable of the processes that multiplex digital signalsgenerated according to the clock source signals having differentfrequency errors and different jitter characteristics and further havingdifferent bit rates, and separate and recover the multiplexed signal.Furthermore, this allows the processing apparatus and LSIs that bundlemany transmission channels to be reduced in scale.

B. Embodiment 1

A data multiplexer system according to Embodiment 1 will hereinafter bedescribed.

[Configuration of Transmitter Apparatus]

FIG. 3 shows a functional configuration of a transmitter apparatus 100according to this embodiment.

The transmitter apparatus 100 includes n input channels (TxP1, . . . ,TxPn), n CDRs 1, n FIFOs 3, n block framers 5, a pattern generator 7, amultiplexer 9, a clock source 11, a PLL 13, a clock source 15, a PLL 17,and a single output channel (TxH1).

[Operation of Transmitter Apparatus]

(a) Overview

First, an overview of data processing executed by the transmitterapparatus 100 will be described.

Serial data signals are input into the transmitter apparatus 100 from ninput channels (TxP1, . . . , TxPn). These data signals may have datarates whose original clocks are different from each other, or have adata rate completely synchronized with one clock. The serial datasignals are input into CDRs 1 corresponding to the respective channels.The processes thereafter are executed independently on each of the ndata signals.

The data signal output from the CDR 1 is sequentially processed by theFIFO 3 and the block framer 5. The data signals independently processedby up to the n block framers 5 are input into the multiplexer 9 atrespective independent timings. The multiplexer 9 temporally multiplexesthe n data signals and the synchronization pattern generated by thepattern generator 7 on a bit-by-bit basis, and outputs the multiplexedsignal to a high speed output channel (TxH1).

(b) Detail

Hereinafter, processing operations executed in components configuringthe transmitter apparatus 100 will sequentially be described in detail.

The CDR 1 extracts a clock component from the input serial data signal.The CDR 1 operates on the basis of the high frequency clock suppliedfrom the PLL 13 to recover a recovered clock synchronized with theserial data signal and bit data synchronized with this clock. Therecovered bit data and the recovered clock are supplied to the FIFO 3.

The clock source 11 is a circuit that generates a clock having a naturalfrequency. This frequency is typically set to a frequency that isacquired by dividing, by a constant, the frequency of the data rate ofthe serial data signal assumed to be received by the CDR 1.

The PLL 13 is a circuit generating a clock having a frequency exactlyconstant times the frequency of the reference clock received from theclock source 11. In this embodiment, the PLL 13 and the clock source 11are provided for each channel corresponding to the serial data signal tobe input. However, a configuration provided with only a single uniformedpair of PLL and the clock source may be adopted.

The FIFO 3 receives the bit data and the recovered clock from the CDR 1,and stores the data string in the internal FIFO (first in first out)memory in synchronization with the recovered clock. The FIFO 3sequentially reads the data string stored in the FIFO memory insynchronization with the clock supplied from the PLL 17, and transmitsthe string to the block framer 5.

During the readout, if no data is stored in the FIFO memory, the FIFO 3issues “FIFO empty state” notification to the block framer 5. Meanwhile,if the FIFO memory is filled with data, the FIFO 3 issues “FIFO fullstate” notification to the block framer 5. The clock used during readoutis common to all the n block framers 5, and required to be synchronizedwith the clock supplied from the PLL 17.

The block framer 5 sequentially reads the data stored in the FIFO 3, andthen divides the data into blocks having a prescribed size and storesthe blocks in the internal memory. Subsequently, the block framer 5reads the blocks having the prescribed size from the internal memory,and transmits the blocks to the multiplexer 9. FIG. 4 shows a dataformat of the block used by the block framer 5 and the block de-framer31 (FIG. 5).

If the block framer 5 normally reads the data during readout from theFIFO 3, this framer adds an identifier having a value “10” andindicating valid data to the head 61 of the block, and stores the datain the payload 63. If the block framer 5 receives the “FIFO empty state”notification from the FIFO 3, this framer cannot read data from the FIFO3. Accordingly, this framer adds the identifier “01” indicating invaliddata to the head 65 of the block, and stores an invalid data string inthe payload 67. It is preferred that the block framer 5 perform a datascramble process on the data string stored in the payload. This allowsthe DC balance and run length of transmission data to be ensured.

The pattern generator 7 generates a data string having a fixed patternat a prescribed cycle. It is required that this data string beidentifiable as a specific pattern. If the sequentially received datastring includes an error, it is preferred that the error can bedetected. Furthermore, it is preferred that the data string generated bythe pattern generator 7 be a string having ensured DC balance and runlength. A most preferred specific pattern is a PRBS (pseudo random bitsequence) pattern generated according to a higher order polynomial.

The multiplexer 9 temporally multiplexes the serial bit strings receivedfrom the n block framers 5 and the pattern generator 7 on a bit-by-bitbasis. Thus, the multiplexer 9 outputs, as multiplexed data, a serialbit string that is (n+1) times faster than the serial bit string on theinput side. Two clocks used for temporally multiplexing are a lowfrequency clock supplied from the PLL 17 and a high frequency clock thatis correctly (n+1) times faster than the low frequency clock. The lowfrequency clock is for reading data. The high frequency clock is fortransmitting data.

[Configuration of Receiver Apparatus]

FIG. 5 shows a functional block configuration of a receiver apparatusaccording to this embodiment.

A receiver apparatus 105 includes a single input channel (RxP1), a clocksource 21, a PLL 22, a CDR 23, a clock divider 25, a de-multiplexer 27,a pattern synchronizer 29, n block de-framers 31, n FIFOs 33, a clocksource 35, n PLLs 37, n frequency controllers 39, and n output channels(RxP1, . . . , RxPn).

[Operation of Receiver Apparatus]

(a) Overview

An overview of data processing executed by the receiver apparatus 105will be described. The receiver 105 receives a serial data signal fromthe input channel RxH1. This data signal is input into the CDR 23. Adata string recovered by the CDR 23 is converted by the de-multiplexer27 from a serial form into a parallel form. The de-multiplexer 27converts the single piece of serial data into n+1 pieces of serial data.The n pieces of serial data thereamong that do not include a fixedpattern are transmitted to the n block de-framers 31. The single pieceof serial data including the fixed pattern is transmitted to the patternsynchronizer 29.

The block de-framer 31 captures only valid bit data configuring a validblock from the input data string, and stores the data in the FIFO memoryof the FIFO 33. That is, the data in the invalid block and the headerdata are excluded by the block de-framer 31. The FIFO 33 sequentiallyreads the stored data according to the clock signal received from thePLL 37. The read data initially has a data rate identical to that of thedata signal channel (TxP1, . . . , TxPn) of the transmitter apparatus100. Data corresponding to the respective input channels (TxP1, . . . ,TxPn) of the transmitter apparatus 100 are output from the respectiveoutput channels (RxP1, . . . , RxPn) of receiver apparatus 105 that havethe same channel numbers.

(b) Detail

Hereinafter, processing operations executed in components configuringthe receiver apparatus 105 will sequentially be described in detail.

The CDR 23 extracts a clock component from the input serial data signal.The CDR 23 operates on the basis of the high frequency clock suppliedfrom the PLL 22, and recovers a recovered clock synchronized with serialdata signal and bit data synchronized with this clock. The recovered bitdata is supplied to the divider 25. The recovered clock is supplied tothe divider 25 and the de-multiplexer 27.

The clock source 21 is a circuit that generates a clock having a naturalfrequency. This frequency is required to be approximately identical to afrequency that is obtained by dividing the data rate of the serial datasignal output from the transmitter 100 by a constant.

The PLL 22 is a circuit generating a clock having a frequency exactlyconstant times the frequency of the reference clock received from theclock source 21.

The clock divider 25 is a circuit generating a divided clock that isobtained by precisely dividing the recovered clock supplied from the CDR23 by a factor n+1. This divided clock is distributed to thede-multiplexer 27, all the block de-framers 31, all the FIFOs 33, andthe pattern synchronizer 29.

The de-multiplexer 27 receives the high frequency recovered clock fromthe CDR 23 while receiving the low frequency divided clock from theclock divider 25. The de-multiplexer 27 converts the bit data receivedfrom the CDR 23 in the serial form into that in a parallel formaccording to the recovered clock. In this conversion, the position atwhich the bit data is captured in units of n+1 bits according to thereceived order can be changed as with a general barrel shifter circuit.The capturing position is according to designation by the patternsynchronizer 29.

The pattern synchronizer 29 receives bit data strings captured by thede-multiplexer 27 at intervals of n+1 bits. The pattern synchronizer 29verifies the correlation between the received bit data string and thespecific pattern generated by the pattern generator 7 of the transmitter100 (FIG. 3). If the correlation between the bit data string beingcurrently received and the specific pattern is significantly low, thepattern synchronizer 29 issues an instruction of shifting the capturingposition in the de-multiplexer 27 by one bit and verifies thecorrelation again. If the correlation between the bit data strings canbe verified for at least a prescribed time, the pattern synchronizer 29fixes the capturing position of bit data that is to be used in thede-multiplexer 27.

Each block de-framer 31 receives temporally consecutive serial bitstring data from the de-multiplexer 27. Each block de-framer 31identifies the header identifiers “10” and “01” defined by the blockformat from the serial bit string data, and determines the identifiedposition as a boundary of the block format. This allows the block framer5 of the transmitter 100 (FIG. 1) to extract only valid data from thepayload. Subsequently, the block de-framer 31 transmits only the validdata to the FIFO 33.

The FIFO 33 stores the valid data received from the block de-framer 31in the internal FIFO memory. Meanwhile, the FIFO 33 sequentially readsthe stored data according to the clock supplied from the PLL 37. At thistime, if the rate of writing the valid data is equal to the rate ofreading the stored data, the amount of stored data is averaged to zero.Accordingly, the FIFO 33 normally operates. If the rate of writing ishigher than the rate of reading, the FIFO memory runs out of space,causing an overflow occurs. If the rate of writing is lower than therate of reading, data shortage occurs, causing an underflow. The FIFO 33notifies the frequency controller 39 of the OF or UF status and thecurrent remaining amount of stored data.

The clock source 35 is a circuit that generates a reference clock havinga natural frequency. This frequency preferably has a rate that isobtained by dividing the high frequency clock generated by the PLL 37 bya constant.

The PLL 37 is a circuit that generates a high frequency clock having afrequency that is obtained by multiplying the reference clock receivedfrom the clock source 35 by the number of divisions notified from thefrequency controller 39.

The frequency controller 39 monitors the state of the FIFO memory of theFIFO 33 (OF, UF, the remaining amount of stored data), and controls thefrequency of the clock generated by the PLL 37 such that the FIFO 33normally operates. At this time, the frequency controller 39 designatesa division ratio for controlling the frequency of the high frequencyclock generated by the PLL 37, by means of a real number.

FIG. 6 shows a functional block configuration of the PLL 37 used in thereceiver apparatus according to this embodiment. The PLL 37 includes aphase comparator 41, a charge pump 43, a LPF 45, a VCO 47, a clockdivider 49, a selector 51 and a ditherer 53.

The high frequency clock of the PLL 37 is generated by a VCO (voltagecontrolled oscillator) circuit of the VCO 47. As generally known, theVCO circuit is capable of changing the frequency of the clock to begenerated, according to the magnitude of the supplied voltage. The highfrequency clock generated by the VCO 47 is supplied not only to the FIFO33 but also to the clock divider 49.

The clock divider 49 is a circuit for dividing an input high frequencyclock. Through the dividing, this divider generates three divided clockshaving different division ratios. In this embodiment, the three divisionratios are N, N−1 and N+1. Note that N is a natural number at least two.The division ratio may be three ratios, or N, N−M and N+M. Note that Nis a natural number where N>M.

The selector 51 is a circuit that selects any two from among input threedivided clocks and outputs the selected clocks.

The ditherer 53 is a circuit that mixes the input two divided clockssuch that a clock to be output has a division ratio designated by thereal number by the frequency controller 39. Typically, a sigma-deltamodulator circuit is adopted.

The phase comparator 41 is a circuit that compares the phase andfrequency of the clock supplied from the ditherer 53 with those of thereference clock generated by the clock source 35 and generates aninstruction of advancing the phase (up) or an instruction of delayingthe phase (down).

The charge pump 43 is a circuit that converts a digital signal that issupplied from the phase comparator 41 and indicates the instruction ofadvancing the phase (up) or the instruction of delaying the phase(down), into an analog signal with a voltage value (or a current value).This conversion can typically be realized by a charge pump circuit.However, there is another method of realization. Accordingly, thisembodiment does not specify the method of realization.

The LPF 45 is a LPF (low pass filter) circuit that allows only a lowfrequency component of the analog signal of the voltage value (orcurrent value) generated by the charge pump 43 to pass. The LPF circuitis generally widely known. Accordingly, this embodiment does not specifythe detailed configuration. The LPF 45 generates a voltage forcontrolling the frequency of the clock generated by the VCO 47.

FIG. 7 shows an initial control sequence of the PLL 37 according to thefrequency controller 39.

In step S1, the frequency controller 39 sets the division ratio of thePLL 37 to N. In this embodiment, N corresponds to an intermediate valueamong controllable values.

In step S3, the frequency controller 39 resets the remaining amount ofstored data in the FIFO 33, and stops reading the stored data until theremaining amount A of stored data becomes half the amount of data thatcan be stored in the FIFO 33. After the remaining amount of stored datareaches the data amount A, the frequency controller 39 restarts readingthe stored data.

In step S5, the frequency controller 39 monitors the notification of theOF status or the UF status, and measures a time T from the start of stepS5 and to the notification.

In step S7, the frequency controller 39 determines whether therelationship between the measured time T and the data amount A falls inan adjustable range of frequency (preliminarily designated by aspecification of the VCO 47 (FIG. 6)) by the PLL 37 or not. If thefrequency controller 39 determines that the relationship is out of therange, this controller transitions to step S9. If the frequencycontroller 39 determines that the relationship is within the range, thiscontroller transitions to step S15. According to the relationshipbetween the time T and the data amount A here, the time average datarate of the corresponding data flow can be acquired. According to thedata amount, the transmission data rate of the corresponding data flowcan be estimated.

In step S9, the frequency controller 39 determines whether the status ofthe FIFO 33 is the OF status or the UF status. In the case of the UFstatus, the frequency controller 39 transitions to step S11. In the caseof the OF status, the frequency controller 39 transitions to step S13.

In step S11, the frequency controller 39 changes the mode of the PLL 37to a mode for operation at a low speed data rate. Subsequently, thefrequency controller 39 transitions to step S1.

In step S13, the frequency controller 39 changes the mode of the PLL 37to a mode for operation at a high speed data rate. Subsequently, thefrequency controller 39 transitions to step S1.

In step S15, the frequency controller 39 determines whether the statusof the FIFO 33 is the OF status or the UF status. In the case of the UFstatus, the frequency controller 39 transitions to step S17. In the caseof the OF status, the frequency controller 39 transitions to step S19.

In step S17, the frequency controller 39 instructs the selector 51 ofthe PLL 37 to select two ratios, or the division ratio N−1 and thedivision ratio N. Subsequently, the frequency controller 39 transitionsto step S21.

In step S19, the frequency controller 39 instructs the selector 51 ofthe PLL 37 to select two ratios, or the division ratio N and thedivision ratio N+1. Subsequently, the frequency controller 39transitions to step S21.

In step S21, the frequency controller 39 acquires the difference betweenthe high frequency clock according to the division ratio N and the rateof data being currently received, on the basis of the time T measured instep S5 and the storable data amount A. Subsequently, the frequencycontroller 39 transitions to step S23.

In step S23, the frequency controller 39 acquires the division ratio ofthe rate of the data being currently received on the basis of theacquired clock difference, and sets the ditherer 53 of the PLL 33 tothis ratio. Subsequently, the frequency controller 39 transitions tostep S1.

FIG. 8 shows a control sequence of updating the PLL 37 by the frequencycontroller 39. This operation is executed after completion of theinitial control sequence.

In step S31, the frequency controller 39 successively monitors theremaining amount of stored data of the FIFO 33, and acquires thedifference of remaining amounts of data at the last monitoring time andthe current monitoring time. Subsequently, the frequency controller 39transitions to step S33.

In step S33, the frequency controller 39 acquires an elapsed duration(the number of cycles) corresponding to the acquired difference.Subsequently, the frequency controller 39 transitions to step S35.

In step S35, the frequency controller 39 acquires the difference ofclocks between the high frequency clock being currently generated by thePLL 37 and the data rate of the data string being currently received, onthe basis of the difference acquired in step S31 and the elapsedduration acquired in step S33. Subsequently, the frequency controller 39transitions to step S37.

In step S37, the frequency controller 39 acquires a division ratiosuitable for the data rate of the data string being currently receivedon the basis of the clock difference acquired in step S35, and updatesthe setting of the ditherer 53 configuring the PLL 37. Subsequently, thefrequency controller 39 transitions to step S31.

[Advantageous Effects of Embodiment]

Execution of the sequence allows the frequency controller 39 to causethe frequencies of the clocks generated by the PLLs 37 corresponding tothe respective data flows to match with the data rates of the inputchannels on the side of the transmitter apparatus. That is, even in thecase where digital signals having frequency information different fromeach other are input into the respective input channels, the matchingbetween the input channel and the output channel can be ensured.Furthermore, the transmitter apparatus 100 and receiver apparatus 105according to this embodiment are not affected by the content of data ora protocol. This allows the apparatus configuration to be downsized.

C. Embodiment 2

A data multiplexer system according to Embodiment 2 will hereinafter bedescribed. A system according to this embodiment has characteristicscapable of multiplexing data more efficiently than the system accordingto Embodiment 1. This embodiment corresponds to an expanded example ofthe system according to Embodiment 1. Accordingly, only differencestherefrom will be described in the following description.

[Configuration of Transmitter Apparatus]

FIG. 9 shows a functional block configuration of a transmitter apparatus110 according to this embodiment. The transmitter apparatus 110 includesm input channels (TxP1, . . . , TxPm), m CDRs 1, m FIFOs 3, m blockframers 5′, m de-multiplexers 6, a pattern generator 7, a selector 8, amultiplexer 9, a clock source 11, a PLL 13, a clock source 15, a PLL 17,and a single output channel (TxH1).

[Operation of Transmitter Apparatus]

(a) Overview

First, an overview of data processing executed in the transmitterapparatus 110 will be described. The transmitter apparatus 110 receivesdata signals from m input channels (TxP1, . . . , TxPm). These datasignals may have data rates from different clock sources, or a data ratecompletely synchronized with one clock. The m input channels (TxP1, . .. , TxPm) are input into the CDRs 1 corresponding to the respectivechannels. Processes thereafter are executed independently on the m datasignals.

The data signal output from the CDR 1 is sequentially processed by theFIFO 3 and the block framer 5′ in this order. The data independentlyprocessed by up to the m block framers 5′ are input into the mde-multiplexers 6 at respective independent timings. That is, each ofthe m de-multiplexers 6 divides the input data signal into two datasignals. Accordingly, 2m data signals are input into the selector 8.

The selector 8 selects any n data signals from among the 2m datasignals, and transmits the selected signals to the multiplexer 9. Themultiplexer 9 temporally multiplexes the n data signals and asynchronization pattern generated by the pattern generator 7 on abit-by-bit basis, and outputs the multiplexed data to the high speedoutput channel (TxH1).

(b) Detail

Hereinafter, only parts different from those of Embodiment 1 (added ormodified parts) among processing operations executed in the componentsconfiguring the transmitter apparatus 110 will be described.Accordingly, description on parts of the same processing operation andfunction is omitted.

The block framer 5′ sequentially reads data stored in the FIFO 3, andthen divides the data into blocks having a prescribed size and storesthe blocks in the internal memory. Subsequently, the block framer 5′reads the block having the prescribed size from the internal memory, andtransmits the block to the de-multiplexer 6.

FIG. 10 shows the difference of block framing methods executed in theblock framer 5 (FIG. 3) and the block framer 5′

First, FIG. 10 (a) will be described. FIG. 10 (a) shows a processingmethod in the block framer 5 corresponding to that of Embodiment 1. Asdescribed above, the input bandwidth of the FIFO 3 can be changedaccording to the clock frequency recovered by the CDR 1, while theoutput is read in a prescribed bandwidth.

Accordingly, in the case where the input bandwidth of the FIFO 3 isnarrower than the output bandwidth, the FIFO memory becomes in the “FIFOempty state” and the data signal cannot be read from the FIFO memoryuntil a prescribed amount of data is accumulated in the FIFO memory.Thus, the FIFO 3 outputs invalid data during the time period in the“FIFO empty state”. That is, in the case where the difference betweenthe input and output bands, the ratio of invalid data in the output bandincreases, thereby reducing use efficiency.

Next, FIG. 10 (b) will be described. FIG. 10 (b) shows a processingmethod in block framer 5′ that corresponds to that of Embodiment 2. Asdescribed in the drawing, the block framer 5′ can select any of theoutput bands p and 2p (bps). In this embodiment, the output band isselected from the two, or p and 2p. Increase in selection alternativesallows the use efficiency of the band to be improved. The block framer5′ measures a band occupied by valid data, on the data string thatincludes valid data and invalid data and is input from the FIFO 3. Ifthe band of the input valid data is equal to or less than p, the datastring is smoothed such that the output band is p, thereby improving theuse efficiency of the band.

The de-multiplexer 6 includes one input and two outputs, and has afunction of separating the input having a band 2p into two outputs eachhaving a band p. As described above, this separating function stems fromthe capability of the block framer 5′ that selects and outputs one ofthe output with the bandwidth p and the output with the bandwidth 2p.Accordingly, in the case of increasing the types of selectablebandwidths, the separating number is increased according to theselectable bandwidths

The selector 8 includes 2m inputs to which the m de-multiplexers 6 areconnected, and n outputs connected to the multiplexer 9. One inputarbitrarily selected from among the 2m inputs is output from eachoutput.

According to the configuration, in the case where the input band to theblock framer 5′ is narrow, the output band of the block framer 5′ isrestricted to p and only the output of the de-multiplexer 6corresponding to the band p (any one output, in this embodiment) isused. The selector 8 selects only the output used by the de-multiplexer6, thereby allowing the multiplexing efficiency of data in themultiplexer 9 to be improved.

[Configuration of Receiver Apparatus]

FIG. 11 shows a functional block configuration of a receiver apparatusaccording to this embodiment.

The receiver apparatus 115 includes a single input channel (RxH1), aclock source 21, a PLL 22, a CDR 23, a clock divider 25, ade-multiplexer 27, a selector 28, a pattern synchronizer 29, mmultiplexers 30, m block de-framers 31′, m FIFOs 33, a clock source 35,m PLLs 37, m frequency controllers 39, and m output channels (RxP1, . .. , RxPm).

[Operation of Receiver Apparatus]

(a) Overview

An overview of data processing executed by the receiver apparatus 115will be described. The receiver 115 receives a serial data signal froman input channel RxH1. The data signal is input into the CDR 23. A datastring recovered by the CDR 23 is converted by the de-multiplexer 27from a serial form to a parallel form. The de-multiplexer 27 converts asingle piece of serial data into n+1 pieces of serial data. The n piecesof serial data thereamong that do not include the fixed pattern aretransmitted to the selector 28. The one piece of serial data thatincludes the fixed pattern is transmitted to the pattern synchronizer29.

The selector 28 selects any n inputs with respect to 2m outputs, andoutputs the selected inputs to the m multiplexers 30. Each multiplexer30 bundles the two input with a bandwidth p, and transmits outputs witha bandwidth 2p to the corresponding block de-framer 31′. Each blockde-framer 31′ extracts only valid data in the valid block included inthe input, and stores the data in the FIFO memory in the FIFO 33.

Each FIFO 33 sequentially reads the stored data from the FIFO memoryaccording to the clock signal received from the corresponding PLL 37,and outputs the data. The read data is output from the output channel(RxP1, . . . , RxPm) of the receiver apparatus 115 which has a data rateidentical to that of the input channel (TxP1, . . . , TxPm) of thetransmitter apparatus 110 and to which a number identical to that of thecorresponding input channel is assigned.

(b) Detail

Hereinafter, only parts different from those of Embodiment 1 (added ormodified parts) among processing operations executed in the componentsconfiguring the receiver apparatus 115 will be described. Accordingly,description on parts of the same processing operation and function areomitted.

The selector 28 includes n inputs (each having a bandwidth p) connectedfrom the de-multiplexer 27, and 2m outputs (each having a bandwidth p)connected to the m multiplexers 30. The selector 28 is capable ofoutputting one piece of data arbitrarily selected from among the ninputs to each output. However, in the case where the input of themultiplexer 30 subsequent to the selector 28 only uses a bandwidth p,the selector 28 outputs invalid data to an input terminal that themultiplexer 30 does not use.

The multiplexer 30 includes two inputs each having a bandwidth of p, andone output having a bandwidth of 2p. The two inputs are connected to twoof the 2m outputs of the selector 28. The multiplexer 30 multiplexes thetwo inputs and outputs the multiplexed data.

Each block de-framer 31′ receives temporally consecutive serial bitstring data from the multiplexer 30. Each block de-framer 31′ identifiesthe header identifiers “10” and “01” defined by the block format fromthe serial bit string data, and determines that the identified positionas a boundary of the block format. This allows only valid data to beextracted from the payload block-framed by the block framer 5′ of thetransmitter 110. At this time, in the case where the bandwidth in use isp, the block de-framer 31′ converts the bandwidth of the extracted validdata into 2p, and transmits data to the FIFO 33.

[Advantageous Effects of Embodiment]

As described above, according to use of the transmitter apparatus 110 ofthis embodiment, on an input whose bandwidth in actual use is less thanp among the input m data signal channels (TxP1, . . . , TxPm), the datastring is preliminarily smoothed such that the output bandwidth is p,which allows the bandwidth in use for multiplexing to be reduced. Thisenables the data multiplexing efficiency to be improved.

Furthermore, use of the receiver apparatus 115 according to thisembodiment allows the same data rates as those on the data signalchannels (TxP1, . . . , TxPm) on the transmission side to be reproducedon the data signal channels (RxP1, . . . , RxPn) of the respectivecorresponding outputs.

D. Embodiment 3

The above Embodiments 1 and 2 multiplex the channels into the singlechannel. This embodiment is different in that a plurality of channelscan be multiplexed into a plurality of channels. This embodimentcorresponds to an expanded example of the system according toEmbodiment 1. Accordingly, only differences therefrom will be describedin the following description.

[Configuration of Transmitter Apparatus]

FIG. 12 shows a functional block configuration of a transmitterapparatus 120 according to this embodiment.

The transmitter apparatus 120 includes m input channels (TxP1, . . . ,TxPm), m CDRs 1, m FIFOs 3, m block framers 5′, m de-multiplexers 6, apattern generator 7, a selector 8′, q (n+1:1) multiplexers 9, a clocksource 11, a PLL 13, a clock source 15, a PLL 17, and q output channels(TxH1, . . . , TxHq).

In this description and FIG. 12, the description will be made assumingthat q=2 for the sake of simplicity. Furthermore, in this descriptionand FIG. 12, as with Embodiment 2, only the case where thede-multiplexer 6 separates data in a ratio 1:2 will be described.However, the ratio is not limited thereto.

[Operation of Transmitter Apparatus]

(a) Overview

First, an overview of data processing executed in the transmitterapparatus 120 will be described.

The transmitter apparatus 120 receives serial data signals from m inputchannels (TxP1, . . . , TxPm). These data signals may have data ratesfrom different clock sources, or a data rate completely synchronizedwith one clock. The serial data signals are input into the CDRs 1corresponding to the respective channels. The following processes areperformed independently on the m data signals.

The data signal output from the CDR 1 is sequentially processed by theFIFO 3 and the block framer 5′ in this order. The data signalindependently processed by up to the m block framers 5′ is input intothe m de-multiplexers 6 at respective independent timings. Eachde-multiplexer 6 divides one input into two outputs and transmits theoutput to the selector 8′.

The selector 8′ selects any (2×n) from among 2m input signals input fromthe m de-multiplexer 6, and transmits n signals of the selected signalsto each of the two multiplexers 9. Each multiplexer 9 temporallymultiplexes the n data signals supplied from the selector 8′ and thesynchronization pattern generated by the pattern generator 7 on abit-by-bit basis, and outputs the multiplexed data from the high speedoutput channel (TxH1, . . . , TxH2).

(b) Detail

Hereinafter, only parts (added or modified parts) of processingoperations executed by components configuring the transmitter apparatus120 that are different from those of Embodiments 1 and 2 will bedescribed. Accordingly, description on parts of the same processingoperation and function is omitted.

The selector 8′ includes 2m inputs to which the m de-multiplexers 6 areconnected, and (2×n) outputs connected to the two multiplexers 9. Onepiece of data arbitrarily selected from among the 2m inputs is outputfrom each output.

The above configuration allows the data acquired by multiplexing thedata input from the input channels (TxP1, . . . , TxPm) to be output tothe output channels (TxH1, . . . , TxHq) in a distributed manner. Thisallows transmission with a capacity larger than that of transmitterapparatus used in Embodiment 1 or 2.

[Configuration of Receiver Apparatus]

FIG. 13 shows a functional block configuration of a receiver apparatusaccording to this embodiment. The receiver apparatus 125 includes qinput channels (RxH1, . . . , RxHq), a clock source 21, a PLL 22, q CDRs23, a clock divider 25, q deskewing FIFOs 24, a skew controller 26, qde-multiplexers 27, a selector 28′, q pattern synchronizers 29, mmultiplexers 30, m block de-framers 31′, m FIFOs 33, a clock source 35,m PLLs 37, m frequency controllers 39, and m output channels (RxP1, . .. , RxPm).

In this description and FIG. 13, the description will also be madeassuming that q=2 for the sake of simplicity. Furthermore, in thisdescription and FIG. 13, as with Embodiment 2, only the case where themultiplexer 30 combines data in a ratio 2:1 will be described. However,the ratio is not limited thereto.

[Operation of Receiver Apparatus]

(a) Overview

First, an overview of data processing executed in the receiver apparatus125 will be described. The receiver 125 receives serial data signalsfrom two input channels (RxH1 and RxH2). The data signals are input intothe respective corresponding two CDRs 23. The data strings recovered bythe CDRs 23 are stored in the respective corresponding deskewing FIFOs24.

The deskewing FIFOs 24 simultaneously read the stored data stringsaccording to reading control by the skew controller 26 and output therespective corresponding de-multiplexers 27. The de-multiplexer 27converts the received data string from a serial form to a parallel form,and transmits the data to corresponding selector 28′ and the patternsynchronizer 29.

The selector 28′ outputs one input arbitrarily selected from among (2×n)inputs to each of the 2m outputs. Each of the m multiplexers 30 issupplied with two pieces of data among the 2m outputs of the selector28′. Each multiplexer 30 multiplexes the two inputs output from theselector 28′ and outputs the multiplexed data to the corresponding blockde-framer 31′.

Each block de-framer 31 extracts only valid data in the valid blockincluded in each input, and stores the data in the FIFO memory in theFIFO 33.

Each FIFO 33 sequentially reads the stored data from the FIFO memoryaccording to the clock signal received from the corresponding PLL 37,and outputs the data. The read data is output from the output channels(RxP1, . . . , RxPm) of the receiver apparatus 125 which have data ratesidentical to those of the respective input channels (TxP1, . . . , TxPm)of the transmitter apparatus 120 and to which numbers identical to thoseof the respective input channels are assigned.

(b) Detail

Hereinafter, only parts (added or modified parts) of processingoperations executed by components configuring the receiver apparatus 125that are different from those of Embodiments 1 and 2 will be described.Accordingly, description on parts of the same processing operation andfunction is omitted.

The deskewing FIFOs 24 store the received data on the basis of therecovered clocks supplied from the respective corresponding CDRs 23.Note that the received data is read in synchronization with any one ofthe recovered clocks. The reading start position can be changedaccording to an instruction issued by the skew controller 26.

The skew controller 26 monitors the synchronization operations of thetwo pattern synchronizers 29 and acquires skews in the received data inthe temporal axis on the respective input channels. A method preferableto use for acquiring the skew will hereinafter be described.

The two pattern synchronizers 29 receive a common cyclic synchronizationpattern. Accordingly, when the difference of phases of synchronizationpatterns received on the inputs is detected, the difference of phases isequal to the skew. The skew controller 26 always monitors the positionof reading the deskewing FIFO 24 such that the acquired skew becomeszero. Accordingly, on the data strings input into the twode-multiplexers 27, the temporal relationship at the time of beinginitially output from the transmitter apparatus 120 is reproduced.

The selector 28′ includes (2×n) inputs (each having a bandwidth p)connected from two de-multiplexers 27, and 2m outputs (each having abandwidth p) connected to the m multiplexers 30. The selector 28′ cantransmits selected data of any one among the (2×n) inputs to eachoutput. However, in the case where the input of the multiplexer 30 at astage subsequent to the selector 28′ only uses a bandwidth p, theselector 28′ outputs invalid data for the input of the multiplexer 30that is not used.

In general, among pieces of data transferred on the output channels(TxH1, . . . , TxHq) of the transmitter apparatus 120 in a distributedmanner, simultaneous arrival on the side of the receiver apparatus 125is not ensured. However, in the case of this embodiment, the datastrings are input into the respective input channels (RxH1, . . . ,RxHq) of the receiver apparatus 125 and subsequently the skew controller26 and the deskewing FIFOs 24 adjust the temporal relationship to thatat the time of transmission. Accordingly, large capacity transmission incomparison with the cases of Embodiments 1 and 2, and data recovery onthe receiving side can be realized.

E. Another Embodiment

A part or the entire parts of the configurations, functions, processors,processing means and the like may be realized as, for instance,integrated circuits and other hardware. The configurations, functionsand the like may be realized by a processor analyzing and executingprograms that realize respective functions. That is, the configurationsand the functions may be realized as software. Information of programs,tables, files and the like that realize the functions can be stored instoring devices, such as a memory, a hard disk and a SSD (solid statedrive), and storing media, such as an IC card, an SD card and a DVD.

Only control lines and information lines that are required for the sakeof description are indicated. All control lines and information linesthat are required for a product are not completely shown. In actuality,it can be considered that all the configurational components areconnected to each other.

The apparatus, the transmitter apparatus and the receiver apparatusaccording to the present invention are not limited to application ofelectric transmission and optical transmission in the apparatus. Theseapparatuses can be used for mutual connection between apparatuses over along distance, that is, a general long range transmission.

DESCRIPTION OF SYMBOLS

-   100 transmitter apparatus-   105 receiver apparatus-   110 transmitter apparatus-   115 receiver apparatus-   120 transmitter apparatus-   125 receiver apparatus

What is claimed is:
 1. A data multiplexer system comprising: atransmitter apparatus configured to transmit transmission data to atransmission path; and a receiver apparatus configured to receive thetransmission data from the transmission path, wherein the transmitterapparatus comprises: a plurality of input channels, each of which isconfigured to receive transmission data having frequency informationdifferent from frequency information of the other input channels; aplurality of block framers configured to divide transmission datacorresponding to the respective input channels into data blocks having afixed length, as valid data; and a multiplexer configured to multiplexthe data blocks corresponding to the respective input channels andoutput multiplexed data to the transmission path, and the receiverapparatus comprises: a de-multiplexer configured to divide a data stringreceived via the transmission path into as many data flows as the inputchannels on a side of the transmitter apparatus; a plurality of FIFOsconfigured to execute a process of restoring valid data from thecorresponding data flows and storing the data in respective FIFOmemories, and a process of reading the transmission data from therespective FIFO memories and outputting the data to the correspondingoutput channels; and a plurality of frequency controllers configured toexecute a process of estimating transmission data rates from timeaverage data rates of the respective corresponding data flow, and aprocess of adjusting the frequencies of clocks supplied to thecorresponding FIFOs so as to be equal to the respective estimatedtransmission data rates.
 2. The data multiplexer system according toclaim 1, wherein the frequency controller is configured to acquire adifference between the frequency of the clock and the frequency of thetransmission data rate on the basis of a unit time difference in dataamount of the transmission data stored in the FIFO memory separatelyprovided for the data flow, and to adjust the frequency of the clocksuch that the difference is zero.
 3. The data multiplexer systemaccording to claim 1, wherein a PLL circuit generating the clockcomprises an N clock divider, an N−M clock divider, and an N+M clockdivider configured to generate an N divided clock, an N−M divided clock,and an N+M divided clock, respectively, that are defined according tonatural numbers N and M (where N>M), and the frequency controller isconfigured to adjust the frequency of the clock generated by the PLLcircuit, by controlling spreading between a central clock in a frequencyrange defined by the N clock divider, an upper limit clock in thefrequency range defined by the N−M clock divider, and a lower limitclock in the frequency range defined by the N+M clock divider.
 4. Thedata multiplexer system according to claim 1, wherein the block framerhas a function of smoothing a ratio of valid data included in the datablocks corresponding to the data flow, and the de-multiplexer has afunction of reconstructing the data blocks by multiplexing the datastrings corresponding to the same data flow.
 5. The data multiplexersystem according to claim 4, wherein the transmitter apparatus comprisesa plurality of the multiplexers corresponding to the respectivetransmission paths, and a selector configured to assign the data blockscorresponding to the respective input channels to the multiplexers in adistributed manner, and the receiver apparatus comprises a plurality ofsecond FIFO memories corresponding to the respective transmission paths,and a plurality of the de-multiplexers corresponding to the respectivesecond FIFO memories, and the second FIFO memories are configured toread data strings using a clock common to each other and outputs thestrings to the corresponding de-multiplexer.
 6. A receiver apparatus formultiplexing transmission configured to receive multiplexed data inwhich transmission data on a plurality of input channels, each of whichis configured to receive transmission data having frequency informationdifferent from frequency information of the other input channels, ismultiplexed, comprising: a de-multiplexer configured to divide a datastring received via the transmission path into as many data flows as theinput channels on a side of the transmitter apparatus; a plurality ofFIFOs configured to execute a process of restoring valid data from thecorresponding data flows and storing the data in respective FIFOmemories, and a process of reading the transmission data from therespective FIFO memories and outputting the data to the correspondingoutput channels; and a plurality of frequency controllers configured toexecute a process of estimating transmission data rates from timeaverage data rates of the respective corresponding data flow, and aprocess of adjusting the frequencies of clocks supplied to thecorresponding FIFOs so as to be equal to the respective estimatedtransmission data rates.
 7. The receiver apparatus for multiplexingtransmission, according to claim 6, wherein the frequency controller isconfigured to acquire a difference between the frequency of the clockand the frequency of the transmission data rate on the basis of a unittime difference in data amount of the transmission data stored in theFIFO memory separately provided for the data flow, and to adjust thefrequency of the clock such that the difference is zero.
 8. The receiverapparatus for multiplexing transmission, according to claim 6, wherein aPLL circuit generating the clock comprises an N clock divider, an N−Mclock divider, and an N+M clock divider configured to generate an Ndivided clock, an N−M divided clock, and an N+M divided clock,respectively, that are defined according to natural numbers N and M(where N>M), and the frequency controller is configured to adjust thefrequency of the clock generated by the PLL circuit, by controllingspreading between a central clock in a frequency range defined by the Nclock divider, an upper limit clock in the frequency range defined bythe N−M clock divider, and a lower limit clock in the frequency rangedefined by the N+M clock divider.
 9. A transmitter apparatus formultiplexing transmission that transmits multiplexed data via atransmission path, comprising: a plurality of input channels, each ofwhich is configured to receive transmission data having frequencyinformation different from frequency information of the other inputchannels; a plurality of block framers configured to divide transmissiondata, including valid data and invalid data, corresponding to therespective input channels into data blocks having a fixed length, asvalid data, change a bandwidth in accordance with a band ratio of a bandoccupied by the valid data, smooth a ratio of valid data included in thedata blocks corresponding to the data flow, and output the data blocks;and a multiplexer configured to multiplex the data blocks correspondingto the respective input channels and output multiplexed data to thetransmission path.
 10. The transmitter apparatus for multiplexingtransmission according to claim 9, wherein the transmitter apparatuscomprises: a plurality of the multiplexers corresponding to therespective transmission paths; and a selector configured to assign thedata blocks corresponding to the respective input channels to themultiplexers.